The present invention relates to a semiconductor integrated circuit and a standard cell for use in a semiconductor integrated circuit. More particularly, the present invention relates to a standard cell comprising a power source capacitor, a semiconductor integrated circuit comprising the standard cells, and a layout design method for the standard cells.
For recent large-scale semiconductor integrated circuits, for example, an automatic placing and routing technique employing standard cells is widely used in order to design a high-performance semiconductor integrated circuit having an improved operating frequency, low power consumption, and the like in a short period of time. Examples of the standard cell include logic cells (e.g., an inverter circuit, a NAND circuit, an OR circuit, etc.), sequential cells (e.g., a flip-flop circuit, a latch circuit, etc.), and the like. A transistor which is used to construct such a standard cell circuit is herein referred to as a functional transistor.
Next, an exemplary conventional method of designing a semiconductor integrated circuit by automatic placing and routing is illustrated in FIG. 13. In the automatic placing and routing, step S1301 of producing a layout of standard cells which may be used in a netlist is previously performed. The standard cell layout producing step S1301 further includes producing a cell (hereinafter referred to as a power source capacitor cell) which includes only a power source capacitance component (hereinafter referred to as a power source capacitor) with respect to a power source wiring line, but not a functional transistor for a standard cell.
In addition to step S1301, a netlist required to design a semiconductor integrated circuit is logically synthesized (step S1302) from a resistor transfer level (RTL) which is functionally described, using timing constraint information and power consumption information obtained in step S1303. In this case, mapping and optimization of a netlist are performed with respect to cells (e.g.,-a standard cell, a customized cell, etc.). As a standard cell used in this mapping, the standard cell produced in step S1301 is selected. Based on the netlist thus obtained in the logic synthesis step S1302, the standard cells are arranged on a mask (step S1304). Next, in wiring step S1305, wiring is performed between the standard cells to satisfy a connection relationship between each standard cell. Step S1304 and step S1305 are repeated until meeting a specification (e.g., timing, power consumption, etc.). Finally, in step S1306, a space region between each standard cell provided is detected, and a power source capacitor cell is inserted into the detected space region (step S1307). Thus, a semiconductor integrated circuit is completed (step S1308).
Next, a conventional IR-Drop reducing technique will be described. Concerning a standard cell used in automatic placing and routing, the timing of the standard cell can be uniquely determined by applying a constant voltage required for an operation from a power source wiring line which supplies a power source potential when a functional transistor in the standard cell is operated. However, such a power source wiring line has a resistance component, and the voltage of the power source wiring line is transiently changed when a current flows through the functional transistor of the standard cell. Therefore, the applied voltage cannot be always kept constant (hereinafter, such a change is referred to as an IR-Drop, and an instantaneous maximum IR-Drop is represented by a peak IR-Drop). Particularly, when standard cells which are operated with the same timing are cascaded on the same power source wiring line in a semiconductor integrated circuit, the amount of current flowing into these standard cells from the same power source wiring line increases, resulting in a significant IR-Drop. Therefore, the timings of standard cells in the semiconductor integrated circuit are not uniquely determined, highly likely leading to a logically erroneous operation. In this situation, it is a known technique to connect a power source capacitor to a power source wiring line used in a semiconductor integrated circuit to suppress an IR-Drop in order to suppress a sudden IR-Drop in the semiconductor integrated circuit.
Next, a power source capacitor cell used in automatic placing and routing will be described. In automatic placing and routing, the following method is widely used: a power source capacitor cell is previously prepared as a standard cell for use in a semiconductor integrated circuit, and the power source capacitor cell is inserted into a space region in which no standard cell of the semiconductor integrated circuit is provided. However, a standard cell which is likely to logically erroneously operate due to an IR-Drop significantly occurs when a plurality of standard cells are cascaded on the same power source wiring line as described above. Such a standard cell which is likely to logically erroneously operate is often present on a signal path which requires a most strict timing of a semiconductor integrated circuit (hereinafter referred to as a critical path). Particularly, on the critical path, standard cells are arranged as closely as possible to each other in order to reduce the load of a wiring line connecting between each standard cell. A power source capacitor cell required to suppress an IR-Drop in such a densely arranged portion needs to be inserted into the region in which the standard cells are densely arranged. Therefore, in a semiconductor integrated circuit in which a standard cell and a power source capacitor cell are arranged, the area of the semiconductor integrated circuit is increased by an area in which the power source capacitor cell is placed. There is also a conventional technique to calculate the current amount of standard cells and insert a minimally required number of power source capacitor cells. Also in this technique, an area in which a power source capacitor cell is inserted needs to be secured, so that the area of the semiconductor integrated circuit is increased by the area of the power source capacitor cell.
Next, a conventional power source capacitor composed of a MOS transistor will be described with reference to FIG. 14A to 14D. FIG. 14A illustrates a conventional power source capacitor employing an N-channel transistor. In FIG. 14A, 1401 indicates a power source wiring line through which a power source potential is supplied, and 1402 indicates a power source wiring line through which a ground potential is supplied. The power source capacitor is constructed to provide a capacitor between the power source wiring-lines 1401 and 1402. Further, 1403 indicates a contact, 1404 indicates a gate electrode, and 1405 indicates a drain region or a source region of the power source capacitor. FIG. 14B is a cross-sectional view of the power source capacitor, taken along line 14a-14a in an N-channel transistor producible region of FIG. 14A. In FIG. 14B, the gate electrode 1404 of the power source capacitor is connected via the contact 1403 to the power source wiring line 1401 through which the power source potential is supplied, and the drain region or source region 1405 of the power source capacitor is connected via the contact 1403 to the power source wiring line 1402 through which the ground potential is supplied. With such a connection to the power source potential or the ground potential, a channel region 1407 is formed. A first substrate 1409 is connected to the ground potential, and a gate oxide film 1406, which is an insulator, is provided between the gate electrode 1404 and the channel region 1407, so that a power source capacitor 1408 is formed between the gate electrode 1404 and the channel region 1407.
FIG. 14C illustrates a conventional power source capacitor employing a P-channel transistor. In FIG. 14C, 1401 indicates a power source wiring line through which a power source potential is supplied, and 1402 indicates a power source wiring line through which a ground potential is supplied. The power source capacitor is constructed to provide a capacitor with respect to the power source wiring lines 1401 and 1402. Further, 1403 indicates a contact, 1404 indicates a gate electrode, and 1405 indicates a drain region or a source region of the power source capacitor. FIG. 14D is a cross-sectional view of the power source capacitor, taken along line 14b-14b in a P-channel transistor producible region of FIG. 14C. In FIG. 14D, the gate electrode 1404 of the power source capacitor is connected via the contact 1403 to the power source wiring line 1402 through which the ground potential is supplied, and the drain region or the source region 1405 of the power source capacitor is connected via the contact 1403 to the power source wiring line 1401 through which the power source potential is supplied. With such a connection to the power source potential or the ground potential; a channel region 1407 is formed. A substrate 1410 is connected to the ground potential, and a gate oxide film 1406, which is an insulator, is provided between the gate electrode 1404 and the channel region 1407, so that a power source capacitor 1408 is formed between the gate electrode 1404 and the channel region 1407.
Among the above-described conventional techniques, JP 2002-110798 A describes a technique for a semiconductor device and a layout method which employ a power source capacitor, the technique being most similar to the present invention. Hereinafter, a standard cell according to this conventional technique will be described with reference to FIGS. 15A and 15B. In FIG. 15A, 1501 indicates a standard cell, 1502 indicates a P-channel functional transistor region, 1503 indicates an N-channel functional transistor region, 1504 indicates a power source capacitor forming region, 1505 indicates a power source wiring line through which a power source potential is supplied, 1506 indicates a power source wiring line through which a ground potential is supplied, 1507 indicates a left-hand end portion of the functional transistor region 1502, 1508 indicates a left-hand end portion of the functional transistor 1503, 1509 indicates a first power source wiring line resistance, and 1510 indicates a power source wiring line resistance. A power source capacitor is formed in the power source capacitor forming region 1504. In this case, when a functional transistor is operated as described above, since a current flows through the functional transistor, an IR-Drop occurs in the standard 1501 cell due to a resistance possessed by a power source wiring line. Specifically, when a power source capacitor is formed in the power source capacitor forming region 1504 of the standard cell 1501, a current flows from the power source capacitor to the functional transistor 1502 or the functional transistor 1503 via the power source wiring line 1505 through which the power source potential of the standard cell 1501 is supplied or the power source wiring line 1506 through which the ground potential is supplied.
With such a structure, a power source capacitor cell (the power source capacitor forming region 1504) having a power source capacitor can be provided between standard cells for use in a semiconductor integrated circuit, thereby making it possible to reduce the IR-Drop of the standard cell. However, a current path from the power source capacitor which is formed in the power source capacitor forming region 1504 adjacent to the standard cell, to the left-hand end portion 1508 of the functional transistor region 1503 includes the power source wiring line resistance 1509, resulting in a reduction in current from the power source capacitor to the functional transistor.
FIG. 15B illustrates a conventional semiconductor integrated circuit in which standard cells are provided. 1511 indicates a semiconductor integrated circuit, 1512a to 1512f indicate functional transistor regions, 1513 indicates power source capacitor forming regions, 1514a to 1514d indicate power source capacitor unformed regions, and 1515 to 1520 indicate standard cells. In the semiconductor integrated circuit 1511, the standard cell 1515 has a functional transistor in the functional transistor region 1512a and a power source capacitor in the power source capacitor forming region 1513, and the power source capacitor has an effect of reducing an IR-Drop with respect to not only the functional transistor region 1512a in the standard cell 1515 but also the functional transistor region 1512b in the standard cell 1516.
A size of a standard cell will be described. Concerning a standard cell for use in automatic placing and routing, in order to facilitate connection of a power source wiring line or the like between standard cells, at least one of a size in a height direction and a size in a horizontal direction of the standard cell is fixed, while the other size is arbitrarily designed. It is here assumed that the size in the height direction of the standard cell is fixed, while the size in the horizontal direction is variable.
Next, a size of a semiconductor integrated circuit in which standard cells are provided will be described. A size in a horizontal direction of the semiconductor integrated circuit in which the standard cells are provided can be specified with positions of standard cells placed at a left-hand end and a right-hand end of the semiconductor integrated circuit. The size in the horizontal direction of a standard cell can be specified with a region in which a functional transistor is formed. Therefore, the size in the horizontal direction of the semiconductor integrated circuit in which the standard cells are provided can be specified with regions in which functional transistors are formed in the standard cells placed at the left-hand end and the right-hand end of the semiconductor integrated circuit. Also, the size in the vertical direction of the semiconductor integrated circuit in which the standard cells are provided is determined, depending on the number of standard cells arranged in the vertical direction. When it is assumed that the standard cell has a fixed size in the height direction, the size in the height direction of the semiconductor integrated circuit in which the standard cell are provided is uniquely determined.
However, in the conventional standard cell 1501 of FIG. 15A, a portion of the standard cell 1501 which provides the functional transistor 1502 and the functional transistor 1503 is separated from a portion of the standard cell 1501 which provides the power source capacitor forming region 1504. Therefore, when a power source capacitor is constructed in the power source capacitor forming region 1504 of the standard cell 1501, the area of the standard cell is increased by a region in which the power source capacitor is formed.
Further, the conventional structure is equivalent to a structure in which the power source capacitor in the power source capacitor forming region 1504 is provided outside the standard cell. Therefore, for example, when the power source wiring line resistance 1509 from the power source capacitor in the power source capacitor forming region 1504 to the left-hand end portion 1507 of the functional transistor region 1502 in the standard cell 1501 is compared with the power source wiring line resistance 1510 from the power source capacitor in the power source capacitor forming region 1504 to the left-hand end portion 1508 of the functional transistor region 1503 in the standard cell 1501, there is a space region in which no transistor is formed between the functional transistor region 1503 and the power source capacitor forming region 1504, as compared to a region between the functional transistor region 1502 and the power source capacitor forming region 1504. Therefore, the wiring line resistance is wastefully increased by the space region. In other words, an effect of reducing the peak IR-Drop of the left-hand end portion 1508 of the functional transistor region 1503 is reduced.
In addition, when the standard cell which includes a power source capacitor is used in a semiconductor integrated circuit as in conventional techniques, the overall area of the semiconductor integrated circuit is increased.